검색결과 : 8건
| No. | Article |
|---|---|
| 1 |
Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs Koyama M, Casse M, Coquand R, Barraud S, Vizioz C, Comboroure C, Perreau P, Maffini-Alvaro V, Tabone C, Tosti L, Barnola S, Delaye V, Aussenac F, Ghibaudo G, Iwai H, Reimbold G Solid-State Electronics, 84, 46, 2013 |
| 2 |
Scaling of high-kappa/metal-gate TriGate SOI nanowire transistors down to 10 nm width Coquand R, Barraud S, Casse M, Leroux P, Vizioz C, Comboroure C, Perreau P, Ernst E, Samson MP, Maffini-Alvaro V, Tabone C, Barnola S, Munteanu D, Ghibaudo G, Monfray S, Boeuf F, Poiroux T Solid-State Electronics, 88, 32, 2013 |
| 3 |
Parasitic bipolar impact in 32 nm undoped channel Ultra-Thin BOX (UTBOX) and biased Ground Plane FDSOI high-k/metal gate technology Fenouillet-Beranger C, Perreau P, Boulenc P, Tosti L, Barnola S, Andrieu F, Weber O, Beneyton R, Perrot C, de Buttet C, Abbate F, Campidelli Y, Pinzelli L, Gouraud P, Margain A, Peru S, Bourdelle KK, Nguyen BY, Boedt F, Poiroux T, Faynot O, Skotnicki T, Boeuf F Solid-State Electronics, 74, 32, 2012 |
| 4 |
Impact of a 10 nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32 nm node and below Fenouillet-Beranger C, Perreau P, Denorme S, Tosti L, Andrieu F, Weber O, Monfray S, Barnola S, Arvet C, Campidelli Y, Haendler S, Beneyton R, Perrot C, de Buttet C, Gros P, Pham-Nguyen L, Leverd F, Gouraud P, Abbate F, Baron F, Torres A, Laviron C, Pinzelli L, Vetier J, Borowiak C, Margain A, Delprat D, Boedt F, Bourdelle K, Nguyen BY, Faynot O, Skotnicki T Solid-State Electronics, 54(9), 849, 2010 |
| 5 |
Gate-all-around technology: Taking advantage of ballistic transport? Huguenin JL, Bidal G, Denorme S, Fleury D, Loubet N, Pouydebasque A, Perreau P, Leverd F, Barnola S, Beneyton R, Orlando B, Gouraud P, Salvetat T, Clement L, Monfray S, Ghibaudo G, Boeuf F, Skotnicki T Solid-State Electronics, 54(9), 883, 2010 |
| 6 |
FDSOI devices with thin BOX and ground plane integration for 32 nm node and below Fenouillet-Beranger C, Denorme S, Perreau P, Buj C, Faynot O, Andrieu F, Tosti L, Barnola S, Salvetat T, Garros X, Casse M, Allain F, Loubet N, Pham-Nguyen L, Deloffre E, Gros-Jean M, Beneyton R, Laviron C, Marin M, Leyris C, Haendler S, Leverd F, Gouraud P, Scheiblin P, Clement L, Pantel R, Deleonibus S, Skotnicki T Solid-State Electronics, 53(7), 730, 2009 |
| 7 |
Folded fully depleted FET using Silicon-On-Nothing technology as a highly W-scaled planar solution Bidal G, Loubet N, Fenouillet-Beranger C, Denorme S, Perreau P, Fleury D, Clement L, Laviron C, Leverd F, Gouraud P, Barnola S, Beneyton R, Torres A, Duluard C, Chapon JD, Orlando B, Salvetat T, Grosjean M, Deloffre E, Pantel R, Dutartre D, Monfray S, Ghibaudo G, Boeuf F, Skotnicki T Solid-State Electronics, 53(7), 735, 2009 |
| 8 |
Hybrid high resolution lithography (e-beam/deep ultraviolet) and etch process for the fabrication of stacked nanowire metal oxide semiconductor field effect transistors Pauliac-Vaujour S, Comboroure C, Vizioz C, Barnola S, Brianceau P, Alvaro VM, Dupre C, Ernst T Journal of Vacuum Science & Technology B, 26(6), 2583, 2008 |