검색결과 : 5건
| No. | Article |
|---|---|
| 1 |
Self-aligned double patterning process for subtractive Ge fin fabrication at 45-nm pitch Milenin AP, Witters L, Barla K, Thean A Thin Solid Films, 602, 64, 2016 |
| 2 |
A pragmatic design methodology using proper isolation and doping for bulk FinFETs Liao YB, Chiang MH, Lai YS, Hsu WC Solid-State Electronics, 85, 48, 2013 |
| 3 |
Charge based DC compact modeling of bulk FinFET transistor Cerdeira A, Garduno I, Tinoco J, Ritzenthaler R, Franco J, Togo M, Chiarella T, Claeys C Solid-State Electronics, 87, 11, 2013 |
| 4 |
Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques Redolfi A, Kubicek S, Rooyackers R, Kim MS, Sleeckx E, Devriendt K, Shamiryan D, Vandeweyer T, Delande T, Horiguchi N, Togo M, Wouters JMD, Jurczak M, Hoffmann T, Cockburn A, Gravey V, Diehl DL Solid-State Electronics, 71, 106, 2012 |
| 5 |
Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession Chiarella T, Witters L, Mercha A, Kerner C, Rakowski M, Ortolland C, Ragnarsson LA, Parvais B, De Keersgieter A, Kubicek S, Redolfi A, Vrancken C, Brus S, Lauwers A, Absil P, Biesemans S, Hoffmann T Solid-State Electronics, 54(9), 855, 2010 |