검색결과 : 2건
| No. | Article |
|---|---|
| 1 |
Compact model for short-channel symmetric double-gate junctionless transistors Avila-Herrera F, Cerdeira A, Paz BC, Estrada M, Iniguez B, Pavanello MA Solid-State Electronics, 111, 196, 2015 |
| 2 |
Analytical modeling of the gate tunneling leakage for the determination of adequate high-k dielectrics in double-gate SOI MOSFETs at the 22 nm node Darbandy G, Ritzenthaler R, Lime F, Garduno I, Estrada M, Cerdeira A, Iniguez B Solid-State Electronics, 54(10), 1083, 2010 |