검색결과 : 66건
| No. | Article |
|---|---|
| 1 |
28 nm FDSOI analog and RF Figures of Merit at N-2 cryogenic temperatures Esfeh BK, Planes N, Haond M, Raskin JP, Flandre D, Kilchytska V Solid-State Electronics, 159, 77, 2019 |
| 2 |
Optimisation of rear reflectance in ultra-thin CIGS solar cells towards >20% efficiency Poncelet O, Kotipalli R, Vermang B, Macleod A, Francis LA, Flandre D Solar Energy, 146, 443, 2017 |
| 3 |
Addressing the impact of rear surface passivation mechanisms on ultra-thin Cu(In,Ga)Se-2 solar cell performances using SCAPS 1-D model Kotipalli R, Poncelet O, Li G, Zeng Y, Francis LA, Vermang B, Flandre D Solar Energy, 157, 603, 2017 |
| 4 |
An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs based on experimental data, numerical simulations and analytical models Pereira ASN, de Steel G, Planes N, Haond M, Giacomini R, Flandre D, Kilchytska V Solid-State Electronics, 128, 67, 2017 |
| 5 |
RF SOI CMOS technology on 1st and 2nd generation trap-rich high resistivity SOI wafers Esfeh BK, Makovejev S, Basso D, Desbonnets E, Kilchytska V, Flandre D, Raskin JP Solid-State Electronics, 128, 121, 2017 |
| 6 |
Role of Ionic Strength in Staphylococcal Cell Aggregation Vanzieleghem T, Couniot N, Herman-Bausier P, Flandre D, Dufrene YF, Mahillon J Langmuir, 32(29), 7277, 2016 |
| 7 |
Comparison of self-heating and its effect on analogue performance in 28 nm bulk and FDSOI Makovejev S, Planes N, Haond M, Flandre D, Raskin JP, Kilchytska V Solid-State Electronics, 115, 219, 2016 |
| 8 |
A review of special gate coupling effects in long-channel SOI MOSFETs with lightly doped ultra-thin bodies and their compact analytical modeling Rudenko T, Nazarov A, Kilchytska V, Flandre D Solid-State Electronics, 117, 66, 2016 |
| 9 |
Assessment of 28 nm UTBB FD-SOI technology platform for RF applications: Figures of merit and effect of parasitic elements Esfeh BK, Kilchytska V, Barral V, Planes N, Haond M, Flandre D, Raskin JP Solid-State Electronics, 117, 130, 2016 |
| 10 |
On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration de Souza M, Flandre D, Doria RT, Trevisoli R, Pavanello MA Solid-State Electronics, 117, 152, 2016 |