검색결과 : 2건
| No. | Article |
|---|---|
| 1 |
A 60 GOPS/W,-1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology Rossi D, Pullini A, Loi I, Gautschi M, Gurkaynak FK, Bartolini A, Flatresse P, Benini L Solid-State Electronics, 117, 170, 2016 |
| 2 |
Advanced CAD methodology for history effect characterization in partially depleted SOI libraries Liot V, Flatresse P, Fournier JM, Belleville M Solid-State Electronics, 49(9), 1466, 2005 |