검색결과 : 15건
| No. | Article |
|---|---|
| 1 |
A review of special gate coupling effects in long-channel SOI MOSFETs with lightly doped ultra-thin bodies and their compact analytical modeling Rudenko T, Nazarov A, Kilchytska V, Flandre D Solid-State Electronics, 117, 66, 2016 |
| 2 |
On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration de Souza M, Flandre D, Doria RT, Trevisoli R, Pavanello MA Solid-State Electronics, 117, 152, 2016 |
| 3 |
Reliability of ultra-thin buried oxides for multi-V-T FDSOI technology Besnard G, Garros X, Nguyen P, Andrieu F, Reynaud P, Van Den Daele W, Bourdelle KK, Schwarzenbach W, Toffoli A, Kies R, Delprat D, Reimbold G, Cristoloveanu S Solid-State Electronics, 97, 8, 2014 |
| 4 |
Influence of device architecture on junction leakage in low-temperature process FDSOI MOSFETs Sklenard B, Batude P, Rafhay Q, Martin-Bragado I, Xu CQ, Previtali B, Colombeau B, Khaja FA, Cristoloveanu S, Rivallin P, Tavernier C, Poiroux T Solid-State Electronics, 88, 9, 2013 |
| 5 |
Revisited approach for the characterization of Gate Induced Drain Leakage Rafhay Q, Xu CQ, Batude P, Mouis M, Vinet M, Ghibaudo G Solid-State Electronics, 71, 37, 2012 |
| 6 |
A computationally efficient compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates Lu DD, Dunga MV, Lin CH, Niknejad AM, Hu CM Solid-State Electronics, 62(1), 31, 2011 |
| 7 |
Three-dimensional analytic modelling of front and back gate threshold voltages for small geometry fully depleted SOI MOSFET's Meel K, Gopal R, Bhatnagar D Solid-State Electronics, 62(1), 174, 2011 |
| 8 |
High gate voltage drain current leveling off and its low-frequency noise in 65 nm fully-depleted strained and non-strained SOI nMOSFETs LukyanchikovA N, Garbar N, Kudina V, Smolanka A, Lokshin M, Simoen E, Claeys C Solid-State Electronics, 52(5), 801, 2008 |
| 9 |
Impact strain engineering on gate stack quality and reliability Claeys C, Simoen E, Put S, Giusi G, Crupi F Solid-State Electronics, 52(8), 1115, 2008 |
| 10 |
A simple analytical model for the front and back gate threshold voltages of a fully-depleted asymmetric SOI MOSFET Suh CH Solid-State Electronics, 52(8), 1249, 2008 |