| 1 |
Gate-induced drain leakage (GIDL) in MFMIS and MFIS negative capacitance FinFETs
Min J, Choe G, Shin C
Current Applied Physics, 20(11), 1222, 2020 |
| 2 |
Gate-induced drain leakage current characteristics of p-type polycrystalline silicon thin film transistors aged by off-state stress
Park J, Jang KS, Shin DG, Shin M, Yi JS
Solid-State Electronics, 148, 20, 2018 |
| 3 |
Radiation-enhanced gate-induced-drain-leakage current in the 130 nm partially-depleted SOI pMOSFET
Peng C, Hu ZY, Ning BX, Dai LH, Bi DW, Zhang ZX
Solid-State Electronics, 106, 81, 2015 |
| 4 |
Dependence on an oxide trap's location of random telegraph noise (RTN) in GIDL current of n-MOSFET
Gia QN, Yoo SW, Lee H, Shin H
Solid-State Electronics, 92, 20, 2014 |
| 5 |
Characterization and optimization of partially depleted SOI MOSFETs for high power RF switch applications
Im D, Lee K
Solid-State Electronics, 90, 94, 2013 |
| 6 |
Stress engineering and proton radiation influence on off-state leakage current in triple-gate SOI devices
Agopian PGD, Bordallo CCM, Simoen E, Claeys C, Martino JA
Solid-State Electronics, 90, 155, 2013 |
| 7 |
Revisited approach for the characterization of Gate Induced Drain Leakage
Rafhay Q, Xu CQ, Batude P, Mouis M, Vinet M, Ghibaudo G
Solid-State Electronics, 71, 37, 2012 |
| 8 |
5-bit/cell Characteristics using mixed program/erase mechanism in recessed channel non-volatile memory cells
Han KR, Jeong MK, Cho I, Lee JH
Current Applied Physics, 10(1), E2, 2010 |
| 9 |
Suppression of gate-induced drain leakage by optimization of junction profiles in 22 nm and 32 nm SOI nFETs
Schenk A
Solid-State Electronics, 54(2), 115, 2010 |
| 10 |
Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL)
Cho S, Lee JH, O'uchi S, Endo K, Masahara M, Park BG
Solid-State Electronics, 54(10), 1060, 2010 |
