검색결과 : 27건
| No. | Article |
|---|---|
| 1 |
New prospects on high on-current and steep subthreshold slope for innovative Tunnel FET architectures Llorente CD, Colinge JP, Martinie S, Cristoloveanu S, Wan J, Le Royer C, Ghibaudo G, Vinet M Solid-State Electronics, 159, 26, 2019 |
| 2 |
New insights on SOI Tunnel FETs with low-temperature process flow for CoolCube (TM) integration Llorente CD, Le Royer C, Batude P, Fenouillet-Beranger C, Martinie S, Lu CMV, Allain F, Colinge JP, Cristoloveanu S, Ghibaudo G, Vinet M Solid-State Electronics, 144, 78, 2018 |
| 3 |
A review of the Z(2)-FET 1T-DRAM memory: Operation mechanisms and key parameters Cristoloveanu S, Lee KH, Parihar MS, El Dirani H, Lacord J, Martinie S, Le Royer C, Barbe JC, Mescot X, Fonteneau P, Galy P, Gamiz F, Navarro C, Cheng B, Duan M, Adamu-Lema F, Asenov A, Taur Y, Xu Y, Kim YT, Wan J, Bawedin M Solid-State Electronics, 143, 10, 2018 |
| 4 |
Impact of bias conditions on electrical stress and ionizing radiation effects in Si-based TFETs Ding LL, Gnani E, Gerardin S, Bagatin M, Driussi F, Selmi L, Le Royer C, Paccagnella A Solid-State Electronics, 115, 146, 2016 |
| 5 |
Investigation of ambipolar signature in SiGeOI homojunction tunnel FETs Hutin L, Oeflein RP, Borrel J, Martinie S, Tabone C, Le Royer C, Vinet M Solid-State Electronics, 115, 160, 2016 |
| 6 |
Fabrication and electrical characterizations of SGOI tunnel FETs with gate length down to 50 nm Le Royer C, Villalon A, Hutin L, Martinie S, Nguyen P, Barraud S, Glowacki F, Allain F, Bernier N, Cristoloveanu S, Vinet M Solid-State Electronics, 115, 167, 2016 |
| 7 |
A review of the mechanical stressors efficiency applied to the ultra-thin body & buried oxide fully depleted silicon on insulator technology Morin P, Maitrejean S, Allibert F, Augendre E, Liu Q, Loubet N, Grenouillet L, Pofelski A, Chen KG, Khakifirooz A, Wacquez R, Reboh S, Bonnevialle A, le Royer C, Morand Y, Kanyandekwe J, Chanemougamme D, Mignot Y, Escarabajal Y, Lherron B, Chafik F, Pilorget S, Caubet P, Vinet M, Clement L, Desalvo B, Doris B, Kleemeier W Solid-State Electronics, 117, 100, 2016 |
| 8 |
Extra-low parasitic gate-to-contacts capacitance architecture for sub-14 nm transistor nodes Niebojewski H, Le Royer C, Morand Y, Rozeau O, Jaud MA, Dubois E, Poiroux T, Bensahel D Solid-State Electronics, 97, 45, 2014 |
| 9 |
Ultrathin (5 nm) SiGe-On-Insulator with high compressive strain (-2 GPa): From fabrication (Ge enrichment process) to in-depth characterizations Glowacki E, Le Royer C, Morand Y, Pedini JM, Denneulin T, Cooper D, Barnes JP, Nguyen P, Rouchon D, Hartmann JM, Gourhant O, Baylac E, Campidelli Y, Barge D, Bonnin O, Schwarzenbach W Solid-State Electronics, 97, 82, 2014 |
| 10 |
Progress in Z(2)-FET 1T-DRAM: Retention time, writing modes, selective array operation, and dual bit storage Wan J, Le Royer C, Zaslavsky A, Cristoloveanu S Solid-State Electronics, 84, 147, 2013 |