검색결과 : 4건
| No. | Article |
|---|---|
| 1 |
Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction Tunnel-FETs Vandooren A, Leonelli D, Rooyackers R, Hikavyy A, Devriendt K, Demand M, Loo R, Groeseneken G, Huyghebaert C Solid-State Electronics, 83, 50, 2013 |
| 2 |
Impact of process and geometrical parameters on the electrical characteristics of vertical nanowire silicon n-TFETs Vandooren A, Leonelli D, Rooyackers R, Arstila K, Groeseneken G, Huyghebaert C Solid-State Electronics, 72, 82, 2012 |
| 3 |
Temperature impact on the tunnel fet off-state current components Agopian PGD, Martino MD, dos Santos SG, Martino JA, Rooyackers R, Leonelli D, Claeys C Solid-State Electronics, 78, 141, 2012 |
| 4 |
Drive current enhancement in p-tunnel FETs by optimization of the process conditions Leonelli D, Vandooren A, Rooyackers R, De Gendt S, Heyns MM, Groeseneken G Solid-State Electronics, 65-66, 28, 2011 |