검색결과 : 20건
| No. | Article |
|---|---|
| 1 |
Special Issue: Planar Fully-Depleted SOI technology Foreword Allibert F, Hiramoto T, Nguyen BY Solid-State Electronics, 117, 1, 2016 |
| 2 |
Ultra-thin body & buried oxide SOI substrate development and qualification for Fully Depleted SOI device with back bias capability Schwarzenbach W, Nguyen BY, Allibert F, Girard C, Maleville C Solid-State Electronics, 117, 2, 2016 |
| 3 |
Understanding and optimizing the floating body retention in FDSOI UTBOX Aoulaiche M, Simoen E, Caillat C, Witters L, Bourdelle KK, Nguyen BY, Martino J, Claeys C, Fazan P, Jurczak M Solid-State Electronics, 117, 123, 2016 |
| 4 |
Strain engineering of ultra-thin silicon-on-insulator structures using through-buried-oxide ion implantation and crystallization Ding YJ, Cheng R, Zhou Q, Du AY, Daval N, Nguyen BY, Yeo YC Solid-State Electronics, 83, 37, 2013 |
| 5 |
Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology Fenouillet-Beranger C, Perreau P, Benoist T, Richier C, Haendler S, Pradelle J, Bustos J, Brun P, Tosti L, Weber O, Andrieu F, Orlando B, Pellissier-Tanon D, Abbate F, Richard C, Beneyton R, Gregoire M, Ducote J, Gouraud P, Margain A, Borowiak C, Bianchini R, Planes N, Gourvest E, Bourdelle KK, Nguyen BY, Poiroux T, Skotnicki T, Faynot O, Boeuf F Solid-State Electronics, 88, 15, 2013 |
| 6 |
Transistors on hybrid UTBB/Bulk substrates fabricated by local internal BOX dissolution Nguyen P, Andrieu F, Casse M, Tabone C, Perreau P, Lafond D, Dansas H, Tosti L, Veytizou C, Landru D, Kononchuk O, Guiot E, Nguyen BY, Faynot O, Poiroux T Solid-State Electronics, 90, 39, 2013 |
| 7 |
Study of substrate orientations impact on Ultra Thin Buried Oxide (UTBOX) FDSOI High-K Metal gate technology performances Ben Akkez I, Fenouillet-Beranger C, Cros A, Perreau P, Haendler S, Weber O, Andrieu F, Pellissier-Tanon D, Abbate F, Richard C, Beneyton R, Gouraud P, Margain A, Borowiak C, Gourvest E, Bourdelle KK, Nguyen BY, Poiroux T, Skotnicki T, Faynot O, Balestra F, Ghibaudo G, Boeuf F Solid-State Electronics, 90, 143, 2013 |
| 8 |
Parasitic bipolar impact in 32 nm undoped channel Ultra-Thin BOX (UTBOX) and biased Ground Plane FDSOI high-k/metal gate technology Fenouillet-Beranger C, Perreau P, Boulenc P, Tosti L, Barnola S, Andrieu F, Weber O, Beneyton R, Perrot C, de Buttet C, Abbate F, Campidelli Y, Pinzelli L, Gouraud P, Margain A, Peru S, Bourdelle KK, Nguyen BY, Boedt F, Poiroux T, Faynot O, Skotnicki T, Boeuf F Solid-State Electronics, 74, 32, 2012 |
| 9 |
Dual strained channel CMOS in FDSOI architecture: New insights on the device performance Le Royer C, Casse M, Cooper D, Andrieu F, Weber O, Brevard L, Perreau P, Damlencourt JF, Baudot S, Previtali B, Tabone C, Allain F, Scheiblin P, Rauer C, Figuet C, Aulnette C, Daval N, Nguyen BY, Bourdelle KK, Gyani J, Valenza M Solid-State Electronics, 65-66, 9, 2011 |
| 10 |
SOI versus bulk-silicon nanoscale FinFETs Fossum JG, Zhou ZM, Mathew L, Nguyen BY Solid-State Electronics, 54(2), 86, 2010 |