검색결과 : 5건
| No. | Article |
|---|---|
| 1 |
Strained Si and SiGe tunnel-FETs and complementary tunnel-FET inverters with minimum gate lengths of 50 nm Knoll L, Richter S, Nichau A, Trellenkamp S, Schafer A, Bourdelle KK, Hartmann JM, Zhao QT, Mantl S Solid-State Electronics, 97, 76, 2014 |
| 2 |
Strained silicon based complementary tunnel-FETs: Steep slope switches for energy efficient electronics Knoll L, Richter S, Nichau A, Trellenkamp S, Schafer A, Wirths S, Blaeser S, Buca D, Bourdelle KK, Zhao QT, Mantl S Solid-State Electronics, 98, 32, 2014 |
| 3 |
LaLuO3 higher-kappa dielectric integration in SOI MOSFETs with a gate-first process Nichau A, Ozben ED, Schnee M, Lopes JMJ, Besmehn A, Luysberg M, Knoll L, Habicht S, Mussmann V, Luptak R, Lenk S, Rubio-Zuazo J, Castro GR, Buca D, Zhao QT, Schubert J, Mantl S Solid-State Electronics, 71, 19, 2012 |
| 4 |
High mobility compressive strained Si0.5Ge0.5 quantum well p-MOSFETs with higher-k/metal-gate Yu W, Zhang B, Zhao QT, Hartmann JM, Buca D, Nichau A, Luptak R, Lopes JM, Lenk S, Luysberg M, Bourdelle KK, Wang X, Mantl S Solid-State Electronics, 62(1), 185, 2011 |
| 5 |
Physicochemical and Electrical Properties of LaLuO3/Ge(100) Structures Submitted to Postdeposition Annealings Radtke C, Krug C, Soares GV, Baumvol IJR, Lopes JMJ, Durgun-Ozben E, Nichau A, Schubert J, Mantl S Electrochemical and Solid State Letters, 13(5), G37, 2010 |