검색결과 : 5건
| No. | Article |
|---|---|
| 1 |
The defect-centric perspective of device and circuit reliability-From gate oxide defects to circuits Kaczer B, Franco J, Weckx P, Roussel PJ, Simicic M, Putcha V, Bury E, Cho M, Degraeve R, Linten D, Groeseneken G, Debacker P, Parvais B, Raghavan P, Catthoor F, Rzepa G, Waltl M, Goes W, Grasser T Solid-State Electronics, 125, 52, 2016 |
| 2 |
Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession Chiarella T, Witters L, Mercha A, Kerner C, Rakowski M, Ortolland C, Ragnarsson LA, Parvais B, De Keersgieter A, Kubicek S, Redolfi A, Vrancken C, Brus S, Lauwers A, Absil P, Biesemans S, Hoffmann T Solid-State Electronics, 54(9), 855, 2010 |
| 3 |
Impact of fin width on digital and analog performances of n-FinFETs Subramanian V, Mercha A, Parvais B, Loo J, Gustin C, Dehan M, Collaert N, Jurczak M, Groeseneken G, Sansen W, Decoutere S Solid-State Electronics, 51(4), 551, 2007 |
| 4 |
Scalable and multibias high frequency modeling of multi-fin FETs Crupi G, Schreurs D, Parvais B, Caddemi A, Mercha A, Decoutere S Solid-State Electronics, 50(11-12), 1780, 2006 |
| 5 |
Fully depleted SOICMOS technology for heterogeneous micropower, high-temperature or RF microsystems Flandre D, Adriaensen S, Akheyar A, Crahay A, Demeus L, Delatte P, Dessard V, Iniguez B, Neve A, Katschmarskyj B, Loumaye P, Laconte J, Martinez I, Picun G, Rauly E, Renaux C, Spote D, Zitout M, Dehan M, Parvais B, Simon P, Vanhoenacker D, Raskin JP Solid-State Electronics, 45(4), 541, 2001 |