검색결과 : 1건
| No. | Article |
|---|---|
| 1 |
Managing annealing pattern effects in 45 nm low power CMOS technology Morin P, Cacho F, Beneyton R, Dumont B, Colin A, Bono H, Villaret A, Josse E, Bianchini R Solid-State Electronics, 54(9), 897, 2010 |
| No. | Article |
|---|---|
| 1 |
Managing annealing pattern effects in 45 nm low power CMOS technology Morin P, Cacho F, Beneyton R, Dumont B, Colin A, Bono H, Villaret A, Josse E, Bianchini R Solid-State Electronics, 54(9), 897, 2010 |