검색결과 : 30건
| No. | Article |
|---|---|
| 1 |
Junctionless nanowire transistors parameters extraction based on drain current measurements Trevisoli R, Doria RT, de Souza M, Barraud S, Pavanello MA Solid-State Electronics, 158, 37, 2019 |
| 2 |
Low temperature influence on performance and transport of Omega-gate p-type SiGe-on-insulator nanowire MOSFETs Paz BC, Casse M, Barraud S, Reimbold G, Vinet M, Faynot O, Pavanello MA Solid-State Electronics, 159, 83, 2019 |
| 3 |
Compact modeling of triple gate junctionless MOSFETs for accurate circuit design in a wide temperature range Pavanello MA, Cerdeira A, Doria RT, Ribeiro TA, Avila-Herrera F, Estrada M Solid-State Electronics, 159, 116, 2019 |
| 4 |
Electrical characterization of vertically stacked p-FET SOI nanowires Paz BC, Casse M, Barraud S, Reimbold G, Vinet M, Faynot O, Pavanello MA Solid-State Electronics, 141, 84, 2018 |
| 5 |
Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs Paz BC, Casse M, Barraud S, Reimbold G, Vinet M, Faynot O, Pavanello MA Solid-State Electronics, 149, 62, 2018 |
| 6 |
Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K Paz BC, Casse M, Barraud S, Reimbold G, Vinet M, Faynot O, Pavanello MA Solid-State Electronics, 128, 60, 2017 |
| 7 |
On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration de Souza M, Flandre D, Doria RT, Trevisoli R, Pavanello MA Solid-State Electronics, 117, 152, 2016 |
| 8 |
Charge-based compact analytical model for triple-gate junctionless nanowire transistors Avila-Herrera F, Paz BC, Cerdeira A, Estrada M, Pavanello MA Solid-State Electronics, 122, 23, 2016 |
| 9 |
Compact model for short-channel symmetric double-gate junctionless transistors Avila-Herrera F, Cerdeira A, Paz BC, Estrada M, Iniguez B, Pavanello MA Solid-State Electronics, 111, 196, 2015 |
| 10 |
Compact core model for Symmetric Double-Gate Junctionless Transistors Cerdeira A, Avila F, Iniguez B, de Souza M, Pavanello MA, Estrada M Solid-State Electronics, 94, 91, 2014 |