검색결과 : 4건
| No. | Article |
|---|---|
| 1 |
RF SOI CMOS technology on 1st and 2nd generation trap-rich high resistivity SOI wafers Esfeh BK, Makovejev S, Basso D, Desbonnets E, Kilchytska V, Flandre D, Raskin JP Solid-State Electronics, 128, 121, 2017 |
| 2 |
Spice-compatible modeling of high injection and propagation of minority carriers in the substrate of Smart Power ICs Stefanucci C, Buccella P, Kayal M, Sallese JM Solid-State Electronics, 105, 21, 2015 |
| 3 |
Design and modeling of Faraday cages for substrate noise isolation Wu JH, del Alamo JA Solid-State Electronics, 85, 6, 2013 |
| 4 |
Modeling non-quasi-static effects in channel thermal noise and induced-gate noise in MOS field-effect transistors Deshpande A, Jindal RP Solid-State Electronics, 52(5), 771, 2008 |