검색결과 : 11건
| No. | Article |
|---|---|
| 1 |
Investigation of ambipolar signature in SiGeOI homojunction tunnel FETs Hutin L, Oeflein RP, Borrel J, Martinie S, Tabone C, Le Royer C, Vinet M Solid-State Electronics, 115, 160, 2016 |
| 2 |
Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs Koyama M, Casse M, Coquand R, Barraud S, Vizioz C, Comboroure C, Perreau P, Maffini-Alvaro V, Tabone C, Tosti L, Barnola S, Delaye V, Aussenac F, Ghibaudo G, Iwai H, Reimbold G Solid-State Electronics, 84, 46, 2013 |
| 3 |
Scaling of high-kappa/metal-gate TriGate SOI nanowire transistors down to 10 nm width Coquand R, Barraud S, Casse M, Leroux P, Vizioz C, Comboroure C, Perreau P, Ernst E, Samson MP, Maffini-Alvaro V, Tabone C, Barnola S, Munteanu D, Ghibaudo G, Monfray S, Boeuf F, Poiroux T Solid-State Electronics, 88, 32, 2013 |
| 4 |
Transistors on hybrid UTBB/Bulk substrates fabricated by local internal BOX dissolution Nguyen P, Andrieu F, Casse M, Tabone C, Perreau P, Lafond D, Dansas H, Tosti L, Veytizou C, Landru D, Kononchuk O, Guiot E, Nguyen BY, Faynot O, Poiroux T Solid-State Electronics, 90, 39, 2013 |
| 5 |
High mobility CMOS: First demonstration of planar GeOI p-FETs with SOI n-FETs Le Royer C, Damlencourt JF, Vincent B, Romanjek K, Le Cunff Y, Grampeix H, Mazzocchi V, Carron V, Nemouchi F, Hartmann JM, Arvet C, Vizioz C, Tabone C, Hutin L, Batude P, Vinet M Solid-State Electronics, 59(1), 2, 2011 |
| 6 |
Dual strained channel CMOS in FDSOI architecture: New insights on the device performance Le Royer C, Casse M, Cooper D, Andrieu F, Weber O, Brevard L, Perreau P, Damlencourt JF, Baudot S, Previtali B, Tabone C, Allain F, Scheiblin P, Rauer C, Figuet C, Aulnette C, Daval N, Nguyen BY, Bourdelle KK, Gyani J, Valenza M Solid-State Electronics, 65-66, 9, 2011 |
| 7 |
Schottky Barrier Height Extraction in Ohmic Regime: Contacts on Fully Processed GeOI Substrates Hutin L, Le Royer C, Tabone C, Delaye V, Nemouchi F, Aussenac F, Clavelier L, Vinet M Journal of the Electrochemical Society, 156(7), H522, 2009 |
| 8 |
High performance 70 nm gate length germanium-on-insulator pMOSFET with high-k/metal gate Romanjek K, Hutin L, Le Royer C, Pouydebasque A, Jaud MA, Tabone C, Augendre E, Sanchez L, Hartmann JM, Grampeix H, Mazzocchi V, Soliveres S, Truche R, Clavelier L, Scheiblin P, Garros X, Reimbold G, Vinet M, Boulanger F, Deleonibus S Solid-State Electronics, 53(7), 723, 2009 |
| 9 |
105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers Le Royer C, Clavelier L, Tabone C, Romanjek K, Deguet C, Sanchez L, Hartmann JM, Roure MC, Grampeix H, Soliveres S, Le Carval G, Truche R, Pouydebasque A, Vinet M, Deleonibus S Solid-State Electronics, 52(9), 1285, 2008 |
| 10 |
Comparative study of the fabricated and simulated Impact Ionization MOS (IMOS) Mayer F, Le Royer C, Le Carval G, Tabone C, Claveller L, Deleonibus S Solid-State Electronics, 51(4), 579, 2007 |