검색결과 : 6건
| No. | Article |
|---|---|
| 1 |
Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs Paz BC, Casse M, Barraud S, Reimbold G, Vinet M, Faynot O, Pavanello MA Solid-State Electronics, 149, 62, 2018 |
| 2 |
Enhanced dynamic threshold voltage UTBB SOI nMOSFETs Sasaki KRA, Manini MB, Simoen E, Claeys C, Martino JA Solid-State Electronics, 112, 19, 2015 |
| 3 |
Experimental study of back gate bias effect and short channel effect in ultra-thin buried oxide tri-gate nanowire MOSFETs Ota K, Saitoh M, Tanaka C, Numata T Solid-State Electronics, 91, 123, 2014 |
| 4 |
Improved retention times in UTBOX nMOSFETs for 1T-DRAM applications Sasaki KRA, Nicoletti T, Almeida LM, dos Santos SD, Nissimoff A, Aoulaiche M, Simoen E, Claeys C, Martino JA Solid-State Electronics, 97, 30, 2014 |
| 5 |
Gate-induced floating-body effect (GIFBE) in fully depleted triple-gate n-MOSFETs Na KI, Cristoloveanu S, Bae YH, Patruno P, Xiong W, Lee JH Solid-State Electronics, 53(2), 150, 2009 |
| 6 |
Subthreshold behavior of triple-gate MOSFETs on SOI material Lemme MC, Mollenhauer T, Henschel W, Wahlbrink T, Baus M, Winkler O, Granzner R, Schwierz F, Spangenberg B, Kurz H Solid-State Electronics, 48(4), 529, 2004 |