검색결과 : 36건
No. | Article |
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1 |
Influence of hetero-gate dielectrics on short-channel effects in scaled tunnel field-effect transistors Chien ND, Vinh LT, Tham HTH, Shih CH Current Applied Physics, 20(12), 1342, 2020 |
2 |
Hetero structure PNPN tunnel FET: Analysis of scaling effects on counter doping Joseph HB, Singh SK, Hariharan RM, Priya PA, Kumar NM, Thiruvadigal DJ Applied Surface Science, 449, 823, 2018 |
3 |
GIDL analysis of the process variation effect in gate-all-around nanowire FET Kim S, Seo Y, Lee J, Kang M, Shin H Solid-State Electronics, 140, 59, 2018 |
4 |
Surface potential based modeling of charge, current, and capacitances in DGTFET including mobile channel charge and ambipolar behaviour Jain P, Yadav C, Agarwal A, Chauhan YS Solid-State Electronics, 134, 74, 2017 |
5 |
Radiation-enhanced gate-induced-drain-leakage current in the 130 nm partially-depleted SOI pMOSFET Peng C, Hu ZY, Ning BX, Dai LH, Bi DW, Zhang ZX Solid-State Electronics, 106, 81, 2015 |
6 |
Universal analytic model for tunnel FET circuit simulation Lu H, Esseni D, Seabaugh A Solid-State Electronics, 108, 110, 2015 |
7 |
Parasitic bipolar effect in ultra-thin FD SOI MOSFETs Liu FY, Ionica I, Bawedin M, Cristoloveanu S Solid-State Electronics, 112, 29, 2015 |
8 |
Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism Martino MD, Neves F, Agopian PGD, Martino JA, Vandooren A, Rooyackers R, Simoen E, Thean A, Claeys C Solid-State Electronics, 112, 51, 2015 |
9 |
Physical insights of body effect and charge degradation in floating-body DRAMs Giusi G Solid-State Electronics, 95, 1, 2014 |
10 |
Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction Tunnel-FETs Vandooren A, Leonelli D, Rooyackers R, Hikavyy A, Devriendt K, Demand M, Loo R, Groeseneken G, Huyghebaert C Solid-State Electronics, 83, 50, 2013 |