검색결과 : 3건
| No. | Article |
|---|---|
| 1 |
Design considerations for integration of Horizontal Current Bipolar Transistor (HCBT) with 0.18 mu m bulk CMOS technology Koricic M, Suligoj T, Mochizuki H, Morita S, Shinomura K, Imai H Solid-State Electronics, 54(10), 1166, 2010 |
| 2 |
The influence of junction depth on short channel effects in vertical sidewall MOSFETs Tan L, Buiu O, Hall S, Gill E, Uchino T, Ashburn P Solid-State Electronics, 52(7), 1002, 2008 |
| 3 |
Subthreshold slope degradation model for localized-charge-trapping based non-volatile memory devices Shappir A, Shacham-Diamand Y, Lucky E, Bloom I, Eitan B Solid-State Electronics, 47(5), 937, 2003 |