검색결과 : 43건
| No. | Article |
|---|---|
| 1 |
Reliable gate stack and substrate parameter extraction based on C-V measurements for 14 nm node FDSOI technology Mohamad B, Leroux C, Rideau D, Haond M, Reimbold G, Ghibaudo G Solid-State Electronics, 128, 10, 2017 |
| 2 |
An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs based on experimental data, numerical simulations and analytical models Pereira ASN, de Steel G, Planes N, Haond M, Giacomini R, Flandre D, Kilchytska V Solid-State Electronics, 128, 67, 2017 |
| 3 |
Characterization and modelling of layout effects in SiGe channel pMOSFETs from 14 nm UTBB FDSOI technology Berthelon R, Andrieu F, Ortolland S, Nicolas R, Poiroux T, Baylac E, Dutartre D, Josse E, Claverie A, Haond M Solid-State Electronics, 128, 72, 2017 |
| 4 |
A review of special gate coupling effects in long-channel SOI MOSFETs with lightly doped ultra-thin bodies and their compact analytical modeling Rudenko T, Nazarov A, Kilchytska V, Flandre D Solid-State Electronics, 117, 66, 2016 |
| 5 |
On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration de Souza M, Flandre D, Doria RT, Trevisoli R, Pavanello MA Solid-State Electronics, 117, 152, 2016 |
| 6 |
Fully-depleted pn-junction solar cells based on layers of Cu2ZnSnS4 (CZTS) and copper-diffused AgInS2 ternary nanocrystals Dasgupta U, Saha SK, Pal AJ Solar Energy Materials and Solar Cells, 124, 79, 2014 |
| 7 |
Reliability of ultra-thin buried oxides for multi-V-T FDSOI technology Besnard G, Garros X, Nguyen P, Andrieu F, Reynaud P, Van Den Daele W, Bourdelle KK, Schwarzenbach W, Toffoli A, Kies R, Delprat D, Reimbold G, Cristoloveanu S Solid-State Electronics, 97, 8, 2014 |
| 8 |
Influence of device architecture on junction leakage in low-temperature process FDSOI MOSFETs Sklenard B, Batude P, Rafhay Q, Martin-Bragado I, Xu CQ, Previtali B, Colombeau B, Khaja FA, Cristoloveanu S, Rivallin P, Tavernier C, Poiroux T Solid-State Electronics, 88, 9, 2013 |
| 9 |
Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology Fenouillet-Beranger C, Perreau P, Benoist T, Richier C, Haendler S, Pradelle J, Bustos J, Brun P, Tosti L, Weber O, Andrieu F, Orlando B, Pellissier-Tanon D, Abbate F, Richard C, Beneyton R, Gregoire M, Ducote J, Gouraud P, Margain A, Borowiak C, Bianchini R, Planes N, Gourvest E, Bourdelle KK, Nguyen BY, Poiroux T, Skotnicki T, Faynot O, Boeuf F Solid-State Electronics, 88, 15, 2013 |
| 10 |
Revisited approach for the characterization of Gate Induced Drain Leakage Rafhay Q, Xu CQ, Batude P, Mouis M, Vinet M, Ghibaudo G Solid-State Electronics, 71, 37, 2012 |