검색결과 : 2건
| No. | Article |
|---|---|
| 1 |
Compact modeling of the subthreshold characteristics of junctionless double-gate FETs including the source/drain extension regions Bae MS, Yun I Solid-State Electronics, 156, 48, 2019 |
| 2 |
Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs: Analytical model and design considerations Kranti A, Armstrong GA Solid-State Electronics, 50(3), 437, 2006 |