As silicon semiconductor technologies need to achieve smaller dimensions, the development of System-on-Chip (SOC) devices with a large variety of functional blocks becomes very difficult to realize. A 3-D stacked package is a promising alternative to improve the performance and density of devices beyond traditional package scaling limits. However, there are many issues related to process integration, thermal management, and reliability of 3-D stacked packages. In this study, the printed circuit board (PCB), silicon carrier and silicon chip are integrated with the ultrasonic bonding method. Die shear tests on the joints were carried out with increasing bonding time and input power to optimize the bonding conditions. The integrated chips were successfully bonded with and without non-conductive film (NCF) using ultrasonic energy. The measured electrical resistance of multi-chip package bonded with NCF was lower than that of multi-chip package bonded without NCF. Thermal cycle and high temperature storage tests were carried out to see if the interface was vulnerable. Cross-sectional features of the bonded interface were inspected using a scanning electron microscope. (C) Koninklijke Brill NV, Leiden, 2011