The electrical characterization, in terms of drain current, of SLS ELA p-channel polysilicon TFTs is investigated. The study was based on the DLTS technique. It was found that drain current is governed by trapping/detrapping mechanisms associated to poly-Si/SiO(2) interface states. This fact is in accordance with the results of stretched exponential analysis applied on switch-ON drain current transients. DC hot carrier measurements under worse ageing condition regime were also conducted. Threshold voltage and transconductance variation revealed that hole injection towards the gate oxide is the prevailing mechanism, while poly-Si/SiO(2) interface degradation seems to be minor. (C) 2009 Elsevier B.V. All rights reserved.