For vertical JFETs in silicon carbide, the use of an buried gate with a lateral channel concept in order to achieve a high blocking gain was shown to result in promising device performance. However, due to field crowding at the edges of the buried p-laver, the breakdown Voltage is reduced compared to fully planar devices which are able to use the bulk breakdown field of 4H-SiC. The following work presents a possibility how to further enhance the breakdown voltage of SiC JFETs with buried layers by implementing a buried layer with optimized shape and doping. Consequently, for a given blocking voltage, the specific on-resistance can be reduced, resulting in lower losses for the device.