In this study we have applied well known trench oxide protection techniques to UMOSFETs that are rated for 10kV as a means of reducing the oxide electric field at breakdown, thus improving oxide reliability in the device. The influence of a p(+) implant under the trench on device performance was investigated, and it was found that while this implant reduced the potential buildup in the trench oxide, the forward characteristics of the device were severely distorted. This was due to the occurrence of the JFET effect as well as quasi-saturation effects at high drain biases.