We report the simulation results of 25μ m half cell pitch vertical type 4H-SiC DiMOSFET using the general-purpose device simulator MINIMOS-NT. The best trade-off between breakdown voltage and on-resistance in terms of BFOM is around 19MW/cm(2) with a p-well spacing 5 μ m. The specific on -resistance, R-ON, sp, simulated with V-GS=10V and V-DS= 1 V at room temperature, is around 22.76m&UOmega; cm(2). An 900V breakdown voltage is simulated with ion-implanted edge termination.