This paper analyses the experimental results of voltage capability (V-BR > 120 V) and output characteristics of a new lateral power P-channel MOS transistors manufactured on a 0.18 mu m SOI CMOS technology by means of TCAD numerical simulations. The proposed LDPMOS structures have an N-type buried layer (NBL) inserted in the P-well drift region with the purpose of increasing the RESURF effectiveness and improving the static characteristics (Ron-sp/V-BR trade-off) and the device switching performance. Some architecture modifications are also proposed in this paper to further improve the performance of fabricated transistors. (C) 2011 Elsevier Ltd. All rights reserved.