This paper presents a TCAD study on the effectiveness of stress techniques on bulk FinFETs and planar nFETs, comparing gate-first and gate-last schemes. It is shown that strained Contact Etch-Stop Layers (CESLs) are about 30-40% less effective in narrow FinFETs than on planar FETs when a gate-first scheme is used. On the other hand, using a gate-last scheme significantly enhances CESL effectiveness both on FinFETs and planar FETs, especially when the device width is scaled. A tensile gate fill material leads to a completely different channel stress configuration in gate-last than in gate-first nFETs. While for gate-first FinFETs, this leads to up to 10% mobility improvement at narrow widths, mobility degradation is predicted when tensile gates are used in a gate-last configuration. For this stressor, FinFETs show a different width dependence than planar FETs due to perpendicular stress in the fin sidewall, leading overall to higher mobilities in FinFETs than in their planar counterparts. (c) 2012 Elsevier Ltd. All rights reserved.