Planar and nanowire (NW) tunneling field effect transistors (TFETs) have been fabricated on ultra thin strained and unstrained SOI with shallow doped nickel disilicide (NiSi2) source and drain (S/D) contacts. We developed a novel, self-aligned process to form the p-i-n TFETs which greatly simplifies their fabrication by tilted dopant implantation using the high-k/metal gate as a shadow mask and dopant segregation. Two methods of dopant segregation are compared: dopant segregation based on the "snow-plough" effect of dopants during silicidation and implantation into the suicide (IS) followed by thermal outdiffusion. High drive currents of up to 60 mu A/mu m of planar p-TFETs were achieved indicating good silicide/silicon tunneling junctions. The non-linear temperature dependence of the inverse subthreshold slope S indicates characteristic TFET behavior. Strained Si NW array n-TFETs with omega shaped HfO2/TiN gates show high drive currents of 7 mu A/mu m @ 1 V V-dd and steep inverse subthreshold slopes with minimum values of <50 mV/dec due to the smaller band gap of strained Si and optimized electrostatics. (C) 2013 Elsevier Ltd. All rights reserved.