P-type and N-type multi-gate vertical thin film transistors (vertical TFTs) have been fabricated, adopting the low-temperature (T <= 600 degrees C) polycrystalline silicon (polysilicon) technology. Stacked heavily-doped polysilicon source and drain are electrically isolated by an insulating barrier. Multi-teeth configuration is defined by reactive ion etching leading to sidewalls formation on which undoped polysilicon active layer is deposited. All the polysilicon layers are deposited from low pressure chemical vapor deposition (LPCVD) technique. Vertical TFTs are designed with multi gates, in order to have a higher equivalent channel width. Different active layer thicknesses have been attempted, and an I-ON/I-OFF ratio slightly higher than 10(5) is obtained. P-type and N-type vertical TFTs have shown symmetric electrical characteristics. Different geometrical parameters have been chosen. I-OFF is proportional to the single channel width, and to the tooth number. I-ON is only proportional to the tooth number. These devices open the way of a CMOS-like technology. (C) 2013 Elsevier Ltd. All rights reserved.