Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology

Fenouillet-Beranger C; Perreau P; Benoist T; Richier C; Haendler S; Pradelle J; Bustos J; Brun P; Tosti L; Weber O; Andrieu F; Orlando B; Pellissier-Tanon D; Abbate F; Richard C; Beneyton R; Gregoire M; Ducote J; Gouraud P; Margain A; Borowiak C; Bianchini R; Planes N; Gourvest E; Bourdelle KK; Nguyen BY; Poiroux T; Skotnicki T; Faynot O; Boeuf F

Solid-State Electronics, Vol.88, 15-20, 2013

DOI10.1016/j.sse.2013.04.008 Export Citation

Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology

Fenouillet-Beranger C, Perreau P, Benoist T, Richier C, Haendler S, Pradelle J, Bustos J, Brun P, Tosti L, Weber O, Andrieu F, Orlando B, Pellissier-Tanon D, Abbate F, Richard C, Beneyton R, Gregoire M, Ducote J, Gouraud P, Margain A, Borowiak C, Bianchini R, Planes N, Gourvest E, Bourdelle KK, Nguyen BY, Poiroux T, Skotnicki T, Faynot O, Boeuf F

In this paper, we study how to boost the performance of FDSOI (Fully-Depleted Silicon On Insulator) devices with High-K and Single Metal gate by using the combination of Ultra-Thin Buried Oxide (UTBOX), Ground Plane (GP) and local back biasing integrated with our hybrid process. The interest of local back biasing is highlighted in term of threshold voltage V-T modulation and power management study on the 45 nm 0.374 mu m(2) bitcells and on the ESD functionality as compared to bulk technology. (c) 2013 Elsevier Ltd. All rights reserved.

Keywords:SOI;Fully-depleted;UTBOX;Back bias;ESD;Hybrid process