The impact of compressive and tensile stress on CMOS performance of high-k/metal-gate (HKMG) transistors is studied for < 1 0 0 > and < 1 1 0 > oriented silicon and SiGe channels. The (1 0 0)/< 1 1 0 > channel direction is found to be more stress sensitive for both N- and PMOS whereas the (1 0 0)/< 1 0 0 > oriented transistor has a higher initial hole mobility. These results recommend to use the (1 0 0)/< 1 1 0 > channel orientation for high performance application due to the high drive current gain and (1 0 0)/< 1 0 0 > channel orientation for low power/low cost applications where no stress elements are included to ease the overall process complexity and to decrease costs. SOC level test design implementations show consistent yield as well as improved performance. (c) 2013 Elsevier Ltd. All rights reserved.