Solid-State Electronics, Vol.90, 107-115, 2013
Threshold voltage, and 2D potential modeling within short-channel junctionless DG MOSFETs in subthreshold region
This report focuses on the development of an analytical two-dimensional model to calculate the potential within ultra-scaled junctionless double-gate MOSFETs (DG MOSFETs), which is valid in the subthreshold regime. From that we derive an expression for calculating the threshold voltage of such devices, and present our first results. Compared to conventional MOSFETs, the proposed junctionless transistor has no pn-junctions. Its type of doping in the channel region is the same as in the source/drain regions. The device is turned on by creating a conducting channel in the center of the silicon film, and turned off by depleting it. To achieve good I-on/I-off ratios, and to ensure a safe switching behavior, the investigation of the subthreshold region is therefore important. The analytical model is compared with numerical simulation results from TCAD Sentaurus. Its validity is confirmed for long-channel, as well as for ultra-scaled devices having a channel length about 22 nm. Since the junctionless device is still in its infancy, an analytical model, especially for short-channel devices, can provide help to understand its electrostatic characteristics. (C) 2013 Elsevier Ltd. All rights reserved.
Keywords:Junctionless double-gate (DG) MOSFET;Threshold voltage;Drain-induced barrier lowering;Electrostatic potential;Analytical modeling;Conformal mapping