This paper investigates the front and back gate bias influence on current sense margin and retention time in Ultra-Thin Buried Oxide (UTBOX) Fully Depleted Silicon On Insulator (FDSOI) devices used as a FBRAM (floating body random access memory) cell through simulations and experimental results. This work aims to gain insight into the mechanisms involved into FBRAM operation and optimize the front and back gate biases for achieving the best retention time and current sense margin. The writing '1', through BIT effect, and writing '0', by using capacitive coupling, were verified. We demonstrated that, during the holding, the operation mode of the interfaces is an important factor for the best condition for achieving both a higher current sense margin and a longer retention time, which should be with the front gate in accumulation mode and the back gate in depletion mode. It was also observed that depending on gate bias applied during the hold operation, there are two mechanisms involved in retention time. For less negative gate voltage the retention time is limited by recombination, whereas for more negative gate voltage the generation mechanisms take place. Moreover, the retention time showed more sensitivity to the back gate voltage than the current sense margin. (C) 2013 Elsevier Ltd. All rights reserved.