This work aims to analyze the retention time as a limiting factor for the application of 1T-DRAM cell in future CMOS nodes. Two approaches are proposed in order to improve the retention time: by the source/drain structure engineering or by applying a pulsed back gate bias. This work analyses the upgrade of the retention time by reducing the GIDL effect when the source/drain is underlapped with the gate. A lower retention time is observed for shorter channel length even optimizing the constant back gate bias, but the underlap devices present better results. The Gate-Induced Drain Leakage (GIDL), its amplification by a narrower base of the bipolar transistor inherent in the MOS structure and the longer effective channel length are the responsible mechanisms for the degradation of the retention time in both holding-0 and reading-0. The use of the pulsed back gate bias during write-1, as well as its variation, were analyzed. The pulsed bias case presents an improvement of 5% of the retention time and no difference was observed when the pulsed back gate level was varied. (C) 2014 Elsevier Ltd. All rights reserved.