We investigate the current transport mechanisms in the amorphous silicon/crystalline silicon heterojunction and the change of these processes when an intrinsic amorphous silicon passivation layer with a varying thickness is introduced at the interface. We present analyses of temperature dependent dark current-voltage curves, which allow determining the prevalent current transport path in heterojunction structures. It is shown that the intrinsic passivation layer plays an important role in the current transport in the heterojunction and the thickness of such an interlayer has to be considered when such structures are analyzed. (C) 2014 Elsevier B. V. All rights reserved.