The gate dielectric stack composed of crystalline ZrO2 and Al2O3 buffer layer treated with double nitridation was developed to reduce the capacitance equivalent thickness (CET), leakage current density (J(g)), interfacial state density (D-it), and enhance thermal stability as well. A high dielectric constant of the gate stack was provided by the crystalline ZrO2 with tetragonal/cubic phase. The J(g) and D-it were suppressed by the insertion of the Al2O3 buffer layer treated with remote NH3 plasma nitridation because of the deactivation of the oxygen vacancies and the well passivation of the Si dangling bonds. A further nitridation using remote N-2 plasma on ZrO2 was carried out to reduce the CET and J(g) by the enhancement of the dielectric constant and the deactivation of the grain boundaries and oxygen vacancies. Accordingly, a low CET of 1.09 nm, J(g) of 3.43 x 10(-5) A/cm(2), and D-it of 3.35 x 10(11) cm(-2) eV(-1) were achieved in the crystalline ZrO2/Al2O3 buffer gate stack treated with the double nitridation. The hysteresis was also minimized significantly by the post-deposition annealing at 800 degrees C, which is attributed to the enhanced thermal stability. The results indicate that the crystalline high-K dielectrics/buffer layer with double nitridation treatments is a promising gate stack structure beneficial to the sub-nanometer CET scaling in the future. (C) 2015 Elsevier B.V. All rights reserved.