An analytical model is developed for the bottom-up growth mode observed in the electroplating of high aspect ratio through-silicon vias (TSVs). The effects of various factors, including the feature geometry, the suppression effect of the suppressive additives and the applied electric current, on the filling process are discussed. The process window for void-free filling and its narrowing down with the reduction of TSV footprint are demonstrated in simulation. The motivation to introduce ramping current in the electroplating of high aspect ratio TSVs is analyzed. Reduced plating time is demonstrated for stepwise ramping of the input current. Using the proposed analytical model, a simulation methodology for fast searching of the optimal plating conditions in multiple-step plating schemes is introduced. (C) 2015 The Electrochemical Society. All rights reserved.