This paper demonstrates a low power programmable pulse width LTPS TFT shift register which achieves the constant power consumption over various pulse widths with the smaller number of TFTs compared to the previous programmable shift register. The proposed shift register consists of nine n-channel LTPS TFTs and one coupling capacitor. By eliminating the shoot-through current path in a NOT AND logic, the simulation ensures that the proposed structure reduces the power consumption significantly by 60.5% for two line pulse width and by 88.6% for ten line pulse width from the previous programmable pulse width shift register. The power consumption of 12 shift registers is measured at 0.235 mW, independently of programmed pulse widths. (C) 2014 Elsevier Ltd. All rights reserved.