In this paper, MOSFET layout-dependent gate-around capacitance which include gate-to-source/drain fringing capacitance (C-f) separated from gate-to-contact capacitance (C-co), has been extracted in SPICE model. This work focuses on layout-dependent-effect (LDE) in AC characteristics such as C-f and C-co of MOSFET. To separate C-f and C-co, novel test structures have been designed and fabricated by 40 nm process. According to the silicon data, the apparent variation of C-f with contact to poly space (CPS) and contact to contact space (CCS) has been modeled and exactly extracted. The errors between silicon data and simulation are mainly under 5%. The extraction and modeling of the layout-dependent C-f in this work will contribute high accuracy for digital and RF circuit simulation in advanced CMOS node. (C) 2015 Elsevier Ltd. All rights reserved.