Solid-State Electronics, Vol.113, 138-143, 2015
Impact of the array background pattern on cycling-induced threshold-voltage instabilities in nanoscale NAND Flash memories
This paper highlights that cycling-induced threshold-voltage instabilities in nanoscale NAND Flash technologies display a non-negligible dependence on the background pattern of the memory array during idle/bake periods. Experimental results clearly reveal, in fact, that instabilities in a (victim) cell do not depend only on its memory state, but also on the memory state of its first neighboring (aggressor) cells. The magnitude of this new cell-to-cell interference effect, moreover, appears to depend on the memory state of the victim cell, decreasing with the increase of its threshold-voltage level. From all of the gathered experimental evidence a physical picture explaining the phenomenon is provided, which is, finally, confirmed with the help of numerical simulations. (C) 2015 Elsevier Ltd. All rights reserved.
Keywords:Flash memories;Program/erase cycling;Charge detrapping;Semiconductor device modeling;Semiconductor device reliability