Charge trapping and storage in polymer dielectrics can be harnessed to control semiconductor devices. Organic transistor (OFET) gate insulators affect bias stress and threshold voltage (V-th), and charging them can preset the operating voltages and control bias stress. We describe a chemical design and film fabrication procedure for construction of stacks of polystyrene (PS) layers, each with arbitrary concentrations of potentially chargeable functional groups. Thermal cross-linking of benzocyclobutene subunits ensures layer integrity while keeping the layers free of polar functionality and small molecule byproducts. Neutron reflectivity (NR), scanning electron microscopy, and atomic force microscopy (AFM) showed that individual layer thicknesses varied systematically with polymer concentration in deposition solutions, and interfacial thicknesses ranged from 1.5 to 4 nm, independent of layer thickness, demonstrating formation of distinct layers with minimal roughness or intermixing. The PS-based materials were used as the sole gate dielectrics for pentacene OFETs. We compared V-th before and after charging. Increased bias stress stability as evidenced by reduced V-th shift was seen in devices with trilayer dielectrics with substituted PS as the middle layer compared to a dielectric made from unsubstituted PS. On the other hand, increased V-th shift was seen in many devices with bilayer dielectrics made with substituted PS as the top layer. We attribute the decreased V-th shift seen in trilayer devices to an increased dielectric polarization of the substituted PS in the middle layer that countered the charge trapping effect in the top layer. This demonstration establishes a method for utilizing vertical charge patterns for various electronics applications.