The development of high-voltage MOSFET (HVMOS) is necessary for including power management or radiofrequency functionalities in CMOS technology. In this paper, we investigate the fabrication and optimization of an Extended Drain MOSFET (EDMOS) directly integrated in the ultra-thin SOI film (7 nm) of the 28 nm FDSOI CMOS technology node. Thanks to TCAD simulations, we analyse in detail the device behaviour as a function of the doping level and length of the drift region. The influence of the backplane doping type and of the back-biasing schemes is discussed. DC measurements of fabricated EDMOS samples reveal promising performances in particular in terms of specific on-resistance versus breakdown voltage trade-off. The experimental results indicate that, even in an ultrathin film, the engineering of the drift region could be a lever to obtain integrated HVMOS (3.3-5 V). (C) 2016 Elsevier Ltd. All rights reserved.