Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio (Height/Width = 82.9 nm/8.6 nm) have been developed after integrating a 14 angstrom nitrided gate oxide upon the silicon on insulator (SOI) wafers through an advanced CMOS logic platform. The drive current (I-ON), off current (I-OFF), subthreshold swing (SS), drain-induced barrier lowering (DIBL) and transistor gate delay of 30 nm gate length (L-g) of FinFETs illustrate the promising device performance. The TCAD simulations demonstrate that both threshold voltage (V-th) and off current can be adjusted appropriately through the full silicidation (FUSI) of CoSi2 gate engineering. Moreover, the drive currents of n- and p-channel FinFETs are able to be further enhanced once applying the raised Source/Drain (S/D) approach technology for reducing the S/D resistance drastically. (C) 2016 Elsevier Ltd. All rights reserved.