In this work, new design strategies for 10 nm node NMOS bulk FinFET transistors are investigated to meet low power (LP) (20 pA/mu m < I-OFF < 50 pA/mu m) and ultralow power (ULP) (I-OFF < 20 pA/mu m) requirements using three dimensional (3D) TCAD simulations. The punch-through stop implant, source and drain junction placement and gate workfunction are varied in order to study the impact on the OFF-state current (IOFF), transconductance (gm), gate capacitance (C-gg) and intrinsic frequency (f(T)). It is shown that the gate length of 20 nm for the 10 nm node FinFET can meet the requirements of LP transistors and ULP transistors by source-drain extension engineering, punch-through stop doping concentration, and choice of gate workfunction. (C) 2017 Elsevier Ltd. All rights reserved.