In this work, gate-driven, substrate-triggered and gate-substrate-triggered techniques for both 5 V NMOS-based and 18 V NLDMOS-based power clamps under electrostatic discharge (ESD) stress were investigated in details. Schematics of the three trigger designs were depicted and their physical mechanisms were studied at first. To verify and make comparisons of their performance, they were fabricated in a standard 0.5-mu m 5 V/18 V CDMOS process and characterized by transmission line pulse (TLP) test system, respectively. Experimental results show that 5 V NMOS-based power clamp with substrate-triggered technique has the lowest trigger voltage (similar to 8.37 V) and the highest failure current (similar to 3.58 A), and 18 V gate-substrate-triggered design based on NLDMOS has low trigger voltage (similar to 34.02 V) and greatest robustness (I-t2 = 3.32 A). Therefore, as for low-voltage NMOS-based ESD power clamps, substrate-triggered design obtains the most superior ESD protection performance; but for high-voltage power clamps, gate-substrate-triggered technique can make NLDMOS actualize uniform current conduction and better ESD robustness. (C) 2017 Elsevier Ltd. All rights reserved.