In this paper, new computationally implemented semi-empirical table-based and predictive model for the drain-current in DG-MOS transistors is presented. This model includes two stages; the first one is a generic table-based method to obtain the basic approximate solutions only valid for long channel conditions, the second one calculates the correction to these solutions in order to take into account the short channel effects and it is actually a method that should be calibrated a la carte for each technological parameters set used by manufacturing Integrated Circuits. The new model is valid and continuous in linear, saturation and sub threshold regimes. Short-channel effects and channel-length modulation are accurately predicted by this model that shows very good agreement not only with drain-current curves but also with and their V-DS and V-GS derivatives issued from Silvaco-ATLAS simulations.