A triple self-aligned 2-bit/cell split-gate flash cell with a common select-gate (SG) for 2-bit is produced at 90-nm technology node. In this paper, scaling considerations of this novel split-gate flash are discussed. Firstly, SG-channel length scaling was discussed by evaluating the DIBL effect. It is revealed that aggressive scaling of SGtransistor is acceptable for sub-90-nm 2-bit/cell memory cell, because of the fully isolated SG-channel. Then, floating-gate (FG) coupling ratios are discussed. It is shown that coupling-gate (CG) to FG ratio is comparable to bit-line (BL) to FG ratio. Thirdly, source-side injection has been fully studied to obtain an efficient cell programming with a smaller constant IDP. And an efficient cell programming condition is proposed for scaled 2-bit/cell memory with a constant IDP of 1 mu A/bit. Finally, impact of channel, LDD, and halo implants on I-R10 and I-R01 are discussed. The reliability characteristics are also presented. It was indicated that the scaled cells are very robust.