An improved delayed-signal-cancellation (DSC) phase-locked loop (PLL) is proposed for microgrid applications. The conventionalDSC-PLL suffers fromphase and frequency measurement errors due to a fixed delay operation within the control loop. The source of this error is mathematically analyzed in this paper. Themodified DSC-PLLmodel overcomes the error by using a positive sequence alpha beta detector and a notch filter. The proposed method not only rejects the double frequency oscillation appearing at the output of the PLL under unbalanced loading conditions but also offers good harmonic rejection with nonlinear loads. The proposed model adds minimal complexity to the existing DSC-PLL. To ensure a fast dynamic response as well as a stable operation, a systematic approach is proposed to design the controller gains and filter parameters. The newly designed PLL is simulated and tested for performance verification purposes.