Silicon-on-insulator (SOI) technology based on wafer bonding promises to deliver significant performance advantages and cost reduction over the existing bulk silicon technologies used for making power integrated circuits. A review is presented of the fundamental considerations that arise in the study of SOI devices for high-voltage applications. Significant device design parameters, such as the off-state breakdown voltage, on-state specific resistance, thermal dissipation, packing density, and manufacturability are discussed in the context of the applicable device physics and SOI material requirements. Several possible approaches for achieving high breakdown voltages in SOI devices are described. The advantages and limitations of each approach are discussed and illustrated with some recent results on experimental devices.